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LuminizerTM Key Features
Single configurable hardware platform and multiple applications – Full chip ILT to replace OPC (LuminizerTM; FX) and mask/illumination optimization for cell (LuminizerTM; LE).
  • Configurable, scalable, distributed platform to meet customer’s turn-a-around requirements
  • Full chip product (LuminizerTM FX) to replace full chip OPC
  • LuminizerTM LE is ideal for lithography development and cell optimization, including finding the optimized illumination to give the largest common process window for large arrays of test patterns, mask and illumination optimization for memory core, bit cells, standard cell, etc.
  • Patented Level Set Methods and pixel-based ILT implementation.
  • Fast, rigorous method to solve the lithography inverse problem
  • No need for segmentation scripts
  • Predictable run times
  • Two patents issued, 19 patents pending
  • Simultaneously generate and optimize SRAFs with main features.
  • Single step process for both SRAF generation and main feature correction
  • SRAFs and main features are simultaneously optimized during inversion
  • Mask rule enforced inversion.
  • Supports mask rules including minimum CD, minimum space, minimum area, and minimum segment length
  • Mask rules are enforced during inversion calculation to ensure final mask complies with mask rules
  • All vertices are aligned either vertically or horizontally for mask fracture-friendly design
  • Comprehensive model for each process stage and fast development model solver.
  • Mask, stepper optics, resist development and etching modeled separately
  • Up to 256 Kernels for accurate forward simulation model
  • Fast physical model for resist development (runtime comparable with optical model)
  • Scalar, high-NA scalar, vector models, immersion (hype-NA) model, polarization
  • Process window ILT and integrated process window check.
  • Leverage multiple image planes, including off-focus and off-nominal exposure, and directly optimize depth of focus (DOF) to improve process window
  • Hierarchic repetition extraction improves performance.
  • Always faster than flat run
  • Customer runs show up to 900 X speed-up on memory cores
  • Pixel-based approach to avoid side lobe printing issue.
  • Every pixel is checked, automatically eliminates side lobe printing issue
  • Post OPC verification built into ILT.
  • Calculate the lithography weak point during correction
  • EPE calculation done on every pixel on the polygon edge
  • Calculate EPE at user specified multiple process window anchor points, and generate color map to indicate whether the CD spec is met (feature available on LuminizerTM FX)
  • Comprehensive process window calculation and plots (feature available on LuminizerTM LE)
  • System and user defined topologies give user the flexibility and full control on the level of correction.
  • 5 automatically classified topologies: line-end, inner corner, outer corner, smooth, and other
  • Supports up to 32 layers for user defined critical regions
  • Each topology can have a different EPE tolerance
  • LuminizerTM - Industry’s First Full-Chip Inverse Lithography System For Deep Sub-Wavelength Mask Designs.

    Based on Luminescent’s patented Inverse Lithography Technology (ILT) platform, the Luminizer is an integrated hardware and software replacement for optical proximity correction (OPC) technologies used for sub-wavelength lithography resolution enhancement. Results obtained on printed silicon demonstrate that the Luminizer produces significantly better pattern fidelity and lithography process windows than what is possible with state-of-the-art OPC. In addition, the Luminizer substantially reduces mask-design cycle time for 45- and 32-nm integrated circuit (IC) manufacturing.

    OPC Technologies Stretched Beyond Their Practical Limits

    Despite the emergence of new approaches to overcome lithography-related design constraints, OPC engineers still struggle with the basic challenges of smaller process windows, higher mask costs, and compromised yields at advanced nodes. Even the promise of faster OPC techniques using image-based forward simulation and other new methods fails to solve the inherent accuracy challenges of a process that moves design edges to approximate intended on-wafer results. Furthermore, because OPC is an ad hoc approach, there is no guarantee that if a reticle pattern exists to hit the wafer target, the solution can even be found. OPC is also time-consuming and labor-intensive, requiring extensive script writing and verification, with several mask file respins typically occurring before chipmakers can confidently commit a design to mask and silicon. Moreover, at the 45- and 32-nm nodes, OPC approaches are being stretched beyond their practical limits.

    Conventional approaches approximate the desired on-wafer image with an ad-hoc, iterative, feed-back loop. ILT starts with the desired on-wafer result, mathematically and rigorously solves the lithography inverse problem while also considering mask constraints to obtain the optimal mask
    A New-Generation Resolution Enhancement Technology Solution

    Luminescent’s ILT is the first mask synthesis solution to transition beyond OPC software while fitting seamlessly into existing tape-out flows. It is the only automated resolution enhancement technology (RET) that starts directly with the desired IC pattern on the wafer, explores the entire available optical lithography space by mathematical inversion, and ultimately delivers a mask pattern that generates maximum design fidelity with the broadest possible process window. With its computational speed, the Luminizer is already patterning advanced-node features rendered "extremely difficult-to-print" by OPC techniques. The result: a ground-breaking new-generation RET solution that accelerates lithography yield ramps and reduces time-to-silicon. In addition, the Luminizer enables the use of more-economical 193-nm dry lithography instead of immersion for printing certain 45-nm critical layers and can delay the need for more advanced immersion steppers for 32-nm designs.

    Luminizer fits seamlessly into existing tape-out flows
    ILT: Shattering the 45- and 32-nm Patterning Obstacles

    Luminescent’s ILT is the industry’s first practical inverse algorithmic approach built to overcome the patterning obstacles at the 45- and 32-nm nodes:

    1. Accuracy:ILT enables superior accuracy in four important ways: First, it analyzes the entire image to generate the mask, not just discrete sampling points on the pattern edges. As such, ILT produces optimized mask features that are not locally constrained but are the result of image-quality considerations at locations that are distant by several optical wavelengths. Second, the mask is pre-verified and correct by construction. Third, ILT automatically generates and optimizes assist features during inversion, thus avoiding any special accommodation for assist-feature placement. Finally, ILT enhances accuracy by leveraging state-of-the-art optical and resist models.

    (a)                    (b)
    Simultaneous mask creation and SRAF placement using ILT for a sequence of pitches of clear field line/space patterns. (a) shows the line/space target (black) and ILT generated mask patterns (green/gray), including main features and SRAFs. (b) shows the DOF for through pitch patterns optimized with ILT with and without SRAF
    2. Mask munufacturability:ILT considers mask-writing and inspection rules during the inversion calculation, thereby optimizing the design for manufacturability. Mask rules can be user-specified to meet mask-writing and inspection requirements.

    (a)                    (b)
    Example of ILT mask patterns for isolated contact with different user specified mask rules: (a) min. fragment length 20nm, min. line/space 25nm; (b) min. fragment length 50nm, min. line/space 50nm.

    (a)                    (b)
    An example showing (a) mask pattern calculated with minimum linewidth rule not enforced, and (b) mask pattern calculated with minimum linewidth and space rules enforced.
    3. Ease of use:ILT is pattern-independent for any manufacturing process, which eliminates the extensive, costly scriptwriting requirements that burden OPC software. A highly intuitive user interface cuts the learning curve time significantly.
    4. Speed: ILT’s computation speed is enabled by a combination of fast lithography simulation, patented rapid inversion algorithms and an efficient repetition extraction methodology. These speed enablers are all compatible with massively parallel hardware acceleration.
    A superior approach
    The resolution enhancement revolution
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